Nonvolatile semiconductor memory

ABSTRACT

To propose a new channel structure suitable for high efficiency source side injection, and provide a non-volatile semiconductor memory device and a charge injection method using the same. The non-volatile memory device includes a first conductivity type semiconductor substrate (SUB), a first conductivity type inversion layer-forming region (CH 1 ), second conductivity type accumulation layer-forming regions (ACLa, ACL 2   b ), second conductivity type regions (S/D 1 , S/D 2 ), an insulating film (GD 0 ) and a first conductive layer (CL) formed on the inversion layer-forming region (CH 1 ). A charge accumulation film (GD) and a second conductive layer (WL) are stacked on an upper surface and side surface of the first conductive layer (CL), an exposure surface of the inversion layer-forming region (CH 1 ), and an upper surface of the accumulation layer-forming regions (ACLa, ACLb) and the second conductivity type regions (S/D 1 , S/D 2 ). The second conductive layer (WL) is connected to a word line and second conductivity type regions (S/D 1 , S/D 2 ) are connected to bit lines (Bla, BLb).

TECHNICAL FIELD

[0001] The present invention relates to a non-volatile semiconductormemory device having an impurity arrangement structure and suitable for,for example, high efficiency source side injection and high-speederasure.

BACKGROUND ART

[0002] As flush EEPROMs, there are known a FG (Floating Gate) typeEEPROM wherein a charge accumulation means is comprised of a singleconductive layer, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) typeEEPROM and a MNOS (Metal-Nitride-Oxide-Nitride-Oxide) type EEPROMwherein charge accumulation means are made planarly discreted.

[0003] In the MONOS type memory element, for example, an ONO(Oxide-Nitride-Oxide) film and a gate electrode are stacked on asemiconductor substrate forming a transistor channel, and source anddrain impurity regions having an inversion (a reverse) conductivity typeto that of the channel are formed in the substrate surface region atboth sides of the stacked pattern thereof.

[0004] Then, a charge is injected into a dielectric film (ONO film)having a charge holding faculty from the substrate side to performwriting. When erasing, the held charge is extracted to the substrateside or a charge having an inversion (a reverse) polarity for cancelingthe held charge is injected into the above dielectric film.

[0005] As the charge injection, in addition to utilizing a tunnelphenomenon of a charge in the dielectric film, there is known a methodwherein a charge is energetically excited to a level which the chargeexceeds an insulation barrier of an oxide film of the lowermost layer ofthe ONO film, such as the so-called CHE (Channel-Hot-Electron)injection.

[0006] As one type of the CHE injection method, a source side injectionmethod is known.

[0007] To realize the source side injection method, an electrode forcontrolling a drain side channel and an electrode for controlling asource side channel must be separately provided. The reason for this isto render the drain side channel into a strong inversion (reverse) stateand the source side channel into a weak inversion (reverse) state at thetime of charge injection. At this time, high electric field occurs inthe vicinity of the boundary of both channels thereof, a charge suppliedfrom the source side is excited by this high electric field and injectedfrom the source side to the charge accumulation means of the electrodefor controlling the drain side channel. The injection efficiency isimproved approximately one digit (10 times) more than a normal CHEinjection.

[0008] Progress is being made on low voltage operation due to thedemands of reducing consumption power and miniaturization of size ofelements.

[0009] In the above CHE injection, however, in the case of for examplethe MONOS type memory transistor, it is known the charge injectionefficiency, that is, the ratio of a current I_(G) flowing towards a gateand a current I_(D) flowing towards a drain deteriorates.

[0010] Further, it is notified that the charge injection efficiency ofthe FG type EEPROM is higher than that of the MONOS type EEPROM,however, that efficiency is insufficient. Employing the source sideinjection method further improves the charge injection efficiency,however, there has been encountered a limit in improving the chargeinjection efficiency of the current source side injection method.

DISCLOSURE OF THE INVENTION

[0011] An object of the present invention is to propose a new channelstructure suitable for high efficiency source side injection andhigh-speed data erasure and provide a non-volatile semiconductor memorydevice using the same.

[0012] A non-volatile semiconductor memory device according to a firstaspect of the present invention for achieving the above object,includes: a first conductivity type semiconductor substrate (SUB); afirst conductivity type inversion layer-forming region (CH1) defined ina surface region of the semiconductor substrate (SUB), a channel beingformed by an inversion layer therein; second conductivity typeaccumulation layer-forming regions (ACLa, ACL2 b) formed at least at oneside of the inversion layer-forming region (CH1) in the surface regionof the semiconductor substrate (SUB), channels being formed byaccumulation layers therein; a channel forming region (CH) including theinversion layer-forming region (CH1) and the accumulation layer-formingregions (ACLa, ACLb); a first second conductivity type region (S/D1)formed at one side of the channel forming region (CH) in the surfaceregion of the semiconductor substrate (SUB); a second conductivity typeregion (S/D2) formed at other side of the channel forming region (CH) inthe surface region of the semiconductor substrate (SUB); an insulatingfilm (GD0) formed on the inversion layer-forming region (CH1); a firstconductive layer (CL) formed on the insulating film (GD0); a chargeaccumulation film (GD) having a charge accumulation faculty formed on anupper surface of the first conductive layer (CL), a side surface of astacked portion of the insulating film (GD0) and the first conductivelayer (CL), an exposure surface of the inversion layer-forming region(CH1), an upper surface of the accumulation layer-forming regions (ACLa,ACLb), and an upper surface of the first and second second conductivitytype regions (S/D1, S/D2); and a second conductive layer (WL) formed onthe charge accumulation film (GD); the second conductive layer (WL)being connected to a word line, and the first and second secondconductivity type regions (S/D1, S/D2) being connected to bit lines(Bla, BLb).

[0013] A non-volatile semiconductor memory device according to a secondaspect of the present invention for achieving the above object,includes: a first conductivity type semiconductor substrate (SUB); afirst conductivity type inversion layer-forming region (CH1) defined inthe surface region of the semiconductor substrate (SUB), a channel beingformed by an inversion layer therein; second conductivity typeaccumulation layer-forming regions (ACLa, ACL2 b) formed at least at oneside of the inversion layer-forming region (CH1) in the surface regionof the semiconductor substrate (SUB), channels being formed byaccumulation layers therein; a channel forming region (CH) including theinversion layer-forming region (CH1) and the accumulation layer-formingregions (ACLa, ACLb); a first second conductivity type region (S/D1)formed at one side of the channel forming region (CH) in the surfaceregion of the semiconductor substrate (SUB); a second secondconductivity type region (S/D1) formed at other side of the channelforming region (CH) in the surface region of the semiconductor substrate(SUB); an insulating film (GD0) formed on the inversion layer-formingregion (CH1); a first conductive layer (WG) formed on the insulatingfilm (GD0); a charge accumulation film (GD) having a charge accumulationfaculty formed on a side surface of a stacked portion of the firstconductive layer (WG) and the insulating film (GD0), an exposure surfaceof the inversion layer-forming region (CH1), an upper surface of theaccumulation layer-forming regions (ACLa, ACLb), and an upper surface ofthe first and second second conductivity type regions (S/D1, S/D2); andsecond conductive layers (CLa, CLb) formed on the charge accumulationfilm (GD) at a location above the accumulation layer-forming regions(ACLa, ACLb), the first conductive layer (WG) being connected to a wordline, and the first and second second conductivity type regions (S/D1,S/D2) being connected to bit lines (Bla, BLb).

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a view of an equivalent circuit showing theconfiguration of a non-volatile memory cell according to a firstembodiment of the present invention.

[0015]FIG. 2A is a schematic sectional view taken in the direction alonga word line of the memory cell shown in FIG. 1, and FIG. 2B is a planeview thereof.

[0016]FIG. 3A is an explanatory view of an operation when injectingelectrons into a storage using the source side charge injection method,and FIG. 3B is an explanatory view showing a relationship among ahorizontal position of a channel direction, a channel potential, and achannel electric field of the horizontal direction at this point.

[0017]FIG. 4 is a graph showing results of a device simulation in whicha relationship of a horizontal direction position, an electronconcentration and electric field strength was examined for a case wherean accumulation layer-forming region of a drain side was omitted in theassumption of a memory cell of a structure without an accumulationlayer-forming region.

[0018]FIG. 5 is a graph showing results of a device simulation in whicha horizontal direction position and an electron density and electricfield strength was examined for a case where a semiconductor directlyunder a memory gate has an inverse (a reverse) polarity to asemiconductor directly under a control gate in the assumption of thememory cell according to the first embodiment of the present invention.

[0019]FIG. 6 is a graph showing results of a device simulation in whicha horizontal direction position and an electron density and electricfield strength was examined for a case where N-type semiconductorsdirectly under a memory gate and directly under a control gate haveinverse polarities and a lower concentration than that of FIG. 5 in theassumption of the memory cell according to the first embodiment of thepresent invention.

[0020]FIG. 7 is a graph showing evaluation results of data writingcharacteristics of a prototype memory cell produced under the conditionscorresponding to the model shown in FIG. 4.

[0021]FIG. 8 is a graph showing evaluation results of writingcharacteristics of a prototype memory cell produced under the conditionscorresponding to the model shown in FIG. 5.

[0022]FIG. 9 is a graph showing evaluation results of data writingcharacteristics of a prototype memory cell produced under the conditionscorresponding to the model shown in FIG. 6.

[0023]FIG. 10 is a view showing an operation of a case wherein a chargehaving an inverse polarity to that of a held charge is generated andinjected by utilizing the inter-band tunneling to perform erasure in thememory cell of the first embodiment.

[0024]FIG. 11A is a schematic sectional view in the direction along aword line of a modified example of the memory cell shown in FIG. 2A, andFIG. 11B is a view of an equivalent circuit thereof.

[0025]FIG. 12 is a view of an equivalent circuit showing theconfiguration of a non-volatile memory cell according to a secondembodiment of the present invention.

[0026]FIG. 13A is a schematic sectional view in the direction along aword line of the memory cell shown in FIG. 12, and FIG. 13B is a planeview thereof.

[0027]FIG. 14 is a schematic sectional view in the direction along aword line of a modified example of the memory cell shown in FIG. 13A,and FIG. 14B is a view of an equivalent circuit thereof.

[0028]FIG. 15 is a view showing an operation of a case wherein a chargehaving an inverse polarity to that of a held charge is generated andinjected by a secondary ionization colliding to perform erasure in thememory cell of the second embodiment.

[0029]FIG. 16 is a chart showing bias application conditions in everydata erasure mode of a memory cell in an operation of a memory cell of athird embodiment of the present invention.

[0030]FIG. 17 is a view of a high-energy charge distribution obtainedfrom a simulation of an element structure having an accumulationlayer-forming region.

[0031]FIG. 18 is a view of a high-energy charge distribution obtainedfrom results of performing the same simulation to an element structurewithout an accumulation layer-forming region as an object forcomparison.

[0032]FIG. 19 is a graph showing data erasure characteristics of anoperation of the memory cell of the second embodiment.

[0033]FIG. 20 is a graph showing data erasure characteristics utilizinga conventional type FN tunneling.

[0034]FIG. 21 is a graph showing a drain voltage dependency of athreshold in which a relationship between a size of the ion injectionenergy and erasure speed was examined at the time of forming theaccumulation layer-forming region in the second embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

[0035] First Embodiment

[0036]FIG. 1 is a view of an equivalent circuit of a non-volatile memorycell as a first embodiment of a non-volatile semiconductor memory deviceof the present invention.

[0037] A memory cell M has a three-transistor configuration comprised ofa first memory transistor MT1, a control transistor CT, and a secondmemory transistor MT2, connected in series between 2 lines of bit linesBla, BLb.

[0038] In the memory cell M shown in FIG. 1, gates of the two memorytransistors MT1, MT2 are controlled by a word line WL, while a gate ofthe control transistor CT is controlled by a control line CL.

[0039] An operation voltage is controlled at the time of writing,erasing and reading data, and a column operation controlling means 1 forcontrolling the bit lines BLa, BLb and the control line CL, a rowoperation controlling means 2 for controlling the word line WL, and asubstrate voltage controlling means 3 for controlling a voltage appliedto the substrate are provided as operation controlling means supplied tothe memory cell.

[0040]FIG. 2A is a schematic sectional view taken in the direction alonga word line of the memory cell shown in FIG. 1, and FIG. 2B is a planeview thereof.

[0041] In the memory cell shown in FIG. 2A, reference symbol SUB denotesa base substance (such as a P-type semiconductor substrate, a P-well,and a P-type SOI layer, hereinafter referred to as “substrate”) forforming a semiconductor element and is comprised of a semiconductormaterial such as silicon. In the surface region of the substrate SUB, afirst N-type region (first source/drain region S/D1) and a second N-typeregion (second source/drain region S/D2) formed having N-type impuritiesdoped at a high concentration are formed apart from each other. Thesource/drain regions S/D1 and S/D2, as shown in FIG. 2, are arrangedparallel to each other along in the row direction (ROW). A substratesurface region between the source/drain regions S/D1, S/D2 functions asa channel-forming region CH wherein channels of the memory transistorsMT1, MT2 and the control transistor CH are formed at the time ofoperation. The channel-forming region CH is comprised of a centralchannel-forming region CH1 located approximately at the center and twoside portion channel-forming regions CH2 a, CH2 b located between thecentral channel-forming region CH1 and the two source/drain regionsS/D1, S/D2.

[0042] The central channel-forming region CH1 has a P-type conductivity,that is, the conductivity type of the surface region of the substrateSUB. From the fact that a channel is formed in an inversion layer, thecentral channel-forming region CH1 will hereinafter be referred to as“inversion layer-forming region”.

[0043] Contrary to this, the side portion channel-forming regions CH2 a,CH2 b are comprised of N-type impurity regions ACLa, ACLb having aconcentration (density) lower than the source/drain regions S/D1, S/D2.From the fact that a channel is formed by a large number of carriersaccumulating in the surface of the N-type impurity regions ACLa, ACLb,they will hereinafter be referred to as “accumulation layer-formingregions”. The accumulation layer-forming regions ACLa, ACLb are arrangedat the bottom of the word line WL parallel to each other along thesource/drain S/D1, S/D2.

[0044] A dielectric film (gate insulating film) GD0 comprised of silicondioxide having a thickness of about, for example, 1 nm to 10 nm isformed on the inversion layer-forming region CH1. The gate insulatingfilm GD0 is a single layer and carrier traps inside the film iscomparatively small, so does not have a charge holding faculty.

[0045] A control gate CL comprised of for example polycrystallinesilicon or amorphous silicon doped with impurities is stacked on thegate insulating film GD0 in the same width thereof. The control gate CL,as shown in FIG. 2B, has a width narrower than the width of theinversion layer-forming region CH1 and the spaced distance between theaccumulation layer-forming regions ACLa, ACLb is arranged along in therow direction parallel with the source/drain regions S/D1, S/D2. Thoughthere are no limitations placed on the width of the control gate CL(length of the gate), if made ultrafine to for example 50 nm or less,carriers inside the channel will travel semi-ballistically in thechannel, and so is preferable. Depending on the condition of an electricfield, however, if the gate length is made very fine as such, when acarrier supplied from the source moves inside the channel, a scatteringangle by impurity particle is subjected to a small low-angle scatteringbut not subjected to a high-angle scattering like largely bending anorbit, and so the carrier travels ballistically in the channel.

[0046] A first potential barrier film (bottom potential barrier filmBTM) is formed covering an upper surface and side surface of the controlgate CL stacked on the gate insulating film GD0, a surface of theinversion layer-forming region CH1 wherein the gate insulating film GD0is not formed, surfaces of the accumulation layer-forming regions ACLa,ACLb and surfaces of the source/drain regions S/D1, S/D2. A charge trapfilm CHS is formed on the bottom potential barrier film BTM, and asecond potential barrier film (top potential barrier film TOP) isfurther formed on the charge trap film CHS. The bottom potential barrierfilm BTM, the charge trap film CHS, and the top potential barrier filmTOP comprises a charge accumulation film GD having a chargeaccmumulation faculty.

[0047] For example, a silicon dioxide film formed by thermal oxidationmethod, a silicon dioxide film subjected to nitriding, etc. is used asthe bottom potential barrier film BTM. The film thickness of the bottompotential barrier film BTM is, for example, about 2.5 nm to 6.0 nm.

[0048] The charge trap film CHS is a film serving mainly for capturingand accumulating charges, and is comprised of a silicon nitride film offor example about 3.0 nm to 20 nm thick. The charge trap film CHS isfabricated by for example low pressure CVD (LP-CVD) and contains a largenumber of charge trapping levels therein.

[0049] In the vicinity of an interface with the charge trap film CHS, itis necessary to form deep charge trapping levels at a high density. Forthis purpose, the top potential barrier film TOP is formed by forexample thermal oxidation of a formed charge trap film. The toppotential barrier film TOP may be a HTO(High-Temperature-chemical-vapor-deposited-Oxide) film. When the toppotential barrier film TOP is formed by CVD, deep charge trapping levelsare formed by heat treatment. The film thickness of the top potentialbarrier film TOP needs to be at least 3.0 nm, preferably 3.5 nm or morefor effectively blocking injection of holes from the gate electrode(word line WL) and preventing a decrease of the rewritable number ofdata.

[0050] The word line WL doubling as a gate electrode of a memorytransistor intersecting with the control gate CL is formed on the toppotential barrier film TOP. The word line WL is comprised of for examplepolycrystalline silicon or amorphous silicon doped with impurities.

[0051] In FIG. 2A, the control transistor CT shown in FIG. 1 is formedby the inversion layer-forming region CH1, the accumulationlayer-forming regions ACLa, ACLb, the gate insulating film GD0, and thecontrol gate CL. The memory transistor MT1 shown in FIG. 1 is formed bythe accumulation layer-forming region ACLa, the inversion layer-formingregion CH1, the source/drain region S/D1, and the charge accumulationfilms (GD, BTM, CHS, TOP). The memory transistor MT2 shown in FIG. 1 isformed by the accumulation layer-forming region ACLb, the source/drainregion S/D2, the inversion layer-forming region CH1, and the chargeaccumulation films (GD, BTM, CHS, TOP).

[0052] In the memory cell M, the control transistor CT operatessecondarily in order to improve the charge injection efficiency at thewriting or erasing time of the memory transistors MT1, MT2. Further, dueto the existence of the control transistor CT, regions for injectingcharges are limited. That is, a region for injecting charges in thememory transistor MT1 (hereinafter, referred to as storage 1) is limitedby a portion of the charge accumulation film GD on top of theaccumulation layer-forming region ACLb, and a region for injectingcharges in the memory transistor MT2 (hereinafter, referred to asstorage 2) is limited by a portion of the charge accumulation film GD ontop of the accumulation layer-forming region ACLa. The single-layeredgate insulating film GD0 located between the storage 1 and the storage 2does not have a charge accumulation faculty, so it cannot contribute todata storage. Furthermore, due to the existence of the controltransistor CT, the charges injected into the memory transistors MT1, MT2located on both sides thereof do not interfere among each other, andtherefore two bit storing can be surely performed to the two memorytransistors MT1, MT2.

[0053] Next, an operation of the memory cell M will be explained.

[0054]FIG. 3A is an explanatory view of an operation when injectingelectrons into the storage 1 using the source side charge injectionmethod.

[0055] At the time of writing, the column operation controlling means 1supplies a reference voltage Vs to the second source/drain region S/D2serving as a source and a voltage Vd, for example, 5.0 V, to the firstsource/drain region S/D1 serving as a drain. Further, the columnoperation controlling means supplies a predetermined positive voltageVcg, for example, 1.0 V, to the control gate (control line CL), whilethe row operation controlling means 2 supplies a predetermined positivevoltage Vmg, for example, 7.0 V, to the word line WL. Note that thecontrol line CL illustrated in FIG. 1 corresponds to the control gate.

[0056] Under these conditions, an inversion layer is induced in theinversion layer-forming region CH1, whereby in the vicinity of thesurfaces of the accumulation layer-forming regions ACLa, ACLb at bothsides thereof, an accumulation layer is formed. Electrons from theaccumulation layer formed by the accumulation layer-forming region ACLbof the source side are supplied to the inversion layer induced in theinversion layer-forming region CH1, the supplied electrons areaccelerated in the inversion layer of the inversion layer-forming regionCH1, and a portion thereof turns into high energy electrons (hotelectron) exceeding an energy barrier Φ_(SiO2) of the silicon oxide filmcomprising the bottom potential barrier film BTM at a drain side endportion vicinity P_(P) of the inversion layer-forming region CH1. Aportion of the hot electrons are injected into the storage 1 at acertain probability.

[0057] A relationship among a position Px in a channel direction, achannel potential V, and a channel electric field Ex in a horizontaldirection at this point is shown in FIG. 3B.

[0058] A potential difference between the drain voltage Vd and thesource voltage (reference voltage) Vs is mainly applied to the drainside end portion vicinity P_(P) of the inversion layer-forming regionCH1 positioned between the control gate CL and the accumulationlayer-forming region ACLa of the drain side. As a result, a highelectric field in the channel direction occurs in the drain side endportion vicinity P_(P) of the inversion layer-forming region shown by acurve line Ex_(p).

[0059] The high electric field of the channel direction rapidlyaccelerates the electrons in the inversion layer, and by making theelectrons into high energy electrons, electrons are injected into thestorage 1. For the purpose of improving the injection efficiency ofelectrons, it is good to situate a peak of the electric field Ex_(p) ofthe channel direction in a region where an electric field of the channeland perpendicular direction is as high as possible. This electric fieldcontrol is achieved by changing a value of the voltage supplied to thecontrol gate CL and the word line WL, respectively.

[0060] In the present embodiment, an accumulation layer is formed usingthe accumulation layer-forming region ACLa, and a resistance thereof isreduced. Due to this, a channel resistance at the drain side end portionvicinity P_(P) of the inversion layer-forming region CH1 between thecontrol line CL and the accumulation layer-forming region ACLa becomesrelatively high. Therefore, the potential difference between the drainvoltage Vd and the source voltage Vs converges locally at the drain sideend portion vicinity P_(P) of the inversion layer-forming region CH1 andis supplied. Utilizing this, an electric field of the channel directionis raised at the region P_(P) near a source side end portion of thestorage 1, and due to a potential difference between the word line WLand the drain S/D1, an electric field of the region P_(P) facing thechannel direction and the perpendicular direction running straight israised.

[0061] In the source side charge injection method, the activation energyrequired for electrons to exceed the potential barrier of the bottompotential barrier film BTM is obtained from the electric field of thechannel direction in the region P_(P), near the source side end portionof the storage 1. Further, an electric field of the channel directionand perpendicular direction necessary for injection can be obtained fromthe same region P_(P). Therefore, the charge injection efficiency isimproved more than that of the usual CHE injection.

[0062] Particularly, in the case where the accumulation layer-formingregions ACLa, ACLb are provided as in the present embodiment, byoptimizing the concentration of the N-type impurity of the inversionlayer-forming region CH1 forming the inversion layer and the depth andconcentration (density) of the P-type impurity of the accumulationlayer-forming region ACLa, a degree of freedom of the range of thevoltage applied to the control line CL and the word line WL isincreased, whereby an advantage of easily improving the charge injectionefficiency is attained.

[0063] Contrarily, when performing write to the storage 2, by switchingthe condition of the impress voltage between the two source/drainregions S/D1, S/D2, electrons are efficiently injected into the storage2 by the same operation as above.

[0064] By doing as such, two bits information can be independentlywritten in the memory cell M comprising the two memory transistors MT1,MT2 illustrated in FIG. 1 and FIG. 2.

[0065]FIG. 4 to FIG. 6 are graphs showing results of a device simulationin which a distribution of electron density and electric field strengthin the channel direction were examined in response to whether there isan accumulation layer-forming region ACL or not.

[0066] In the device simulation, a control gate length was set to 0.18μm, a memory gate length to 0.09 μm, a thickness of the chargeaccumulation film GD having charge accumulation faculty to 15 nm, and athickness of the insulating film GD0 underneath the control gate to 10nm, and each of the voltages 5 V was supplied to the word line WL, 1.5 Vto the control gate CL and 3.3 V to the drain (source/drain regionS/D1).

[0067] The abscissa in each of the graphs denotes a position Px in thechannel horizontal direction, and is symmetrical with respect to acenter of the cell as the starting point 0.0. The left side ordinate ineach of the graphs denotes electric field intensities Ex, Ey. In thedrawings, a curve line shown by a dotted line having a large negativepeak denotes a strength of the electric field Ex of the channelhorizontal direction, while a curve line shown by a two-dotted brokenline having a positive peak denotes a strength of the electric field Eyof the channel perpendicular direction. The right side ordinate axis ineach of the graphs denotes an electron density De.

[0068]FIG. 4 shows a case where the accumulation layer-forming regionACLa of the drain side is omitted.

[0069] In this case, since a P-type is used for the substrate SUB,channel-forming regions CH directly under the control gate CL and theword line WL are comprised of a P-type semiconductor.

[0070] The electron density De denoted by a solid line in the graph isthe highest in the source/drain regions S/D, about 5×10²⁰/cm³, the nexthighest in the accumulation layer-forming region ACLb of the source S/D2side, about 8×10¹⁸/cm³, and changes smoothly so that in the inversionlayer-forming region CH1 therebetween, it decreases as it nears thedrain side.

[0071] A direction of the electric field headed for the source S/D2 fromthe drain S/D1 is the heading direction of the electric field, however,since the electrons accelerate in a reverse direction from the directionof the electric field, the channel direction accelerated electric fieldEx of electrons have a negative polarity at the drain side having strongelectric field strength. Since electrons are injected in the directionheaded for the charge accumulation film GD and the gate electrode (wordline WL) from the channel surface, the injection of electrons isassisted more in places where the strength of the perpendiculardirection electric field Ey is stronger. Here, 0.09 μm≦Px≦0.15 μm is aninter-gate gap G between the word line WL portion functioning as amemory gate of the memory transistor at the drain S/D1 side and thecontrol gate CL.

[0072]FIG. 5 and FIG. 6 are graphs showing simulation results on thememory cell according to the present embodiment wherein the conductivitytype of the semiconductor directly under the word line WL portionfunctioning as the memory gate and the conductivity type of thesemiconductor directly under the control gate CL are inversed. Directlyunder the control gate CL is a P-type semiconductor whereas directlyunder the memory gate is an N-type semiconductor due to the presence ofthe accumulation layer-forming regions ACLa, ACLb. In the conditions forion injection when producing the calculation model of FIG. 5, a doseamount was set to 7×10¹² cm⁻² and acceleration energy to 7 keV. Theseconditions correspond to the case of performing ion injection twice.Further, in the ion injection conditions of FIG. 6, dose amount was setto 3.5×10¹² cm⁻² and acceleration energy to 7 keV so that the N-typeimpurity concentration (density) of the semiconductor directly under thememory gate is lower than that of FIG. 5. These conditions correspond tothe case of performing ion injection twice.

[0073] First, attention is directed to the electric field Ex of thechannel horizontal direction. In the graphs of FIG. 5 and FIG. 6, anegative peak of the electric field Ex of the horizontal directionchanges precipitously to about −8.0×10⁵ V/cm or so. Comparing thesegraphs, the electric field Ex in the graph of FIG. 4 does not dropprecipitously, clearly showing that there is no concentration of theelectric field Ex. As a result, the electric field strength is low. Dueto this, in a model corresponding to the conventional memory cellstructure of FIG. 4, there is a lack of electric field Ex forenergetically exciting the electrons, so the probability of generatinghot electrons is lower than in the cases of FIG. 5 and FIG. 6.

[0074] Regarding the electron density De, since directly under thememory gate is a P-type semiconductor in the structure of FIG. 4, whencompared with FIG. 5 and FIG. 6, the electron density is somewhat lower.With respect to this, in the graphs of FIG. 5 and FIG. 6, the channelhorizontal direction electric field Ex drastically declines and theelectron density De near places where the electron acceleration strengthis the greatest, is approximately 1×10¹⁶ cm⁻³.

[0075] Directing attention to the electric field Ey of the channelperpendicular direction, in FIG. 4, given that directly under the memorygate is a P-type semiconductor and the memory gate is a positive bias, adepletion layer expanse to the substrate surface (interface of thecharge accumulation film GD and the substrate SUB) and the electricfield strength Ey of the channel perpendicular direction is strong. Onthe other hand, in FIG. 5 and FIG. 6, the electric field Ey strength ofthe channel perpendicular direction is lower than that of FIG. 4.

[0076] To efficiently inject electrons into the charge accumulation filmGD, it is necessary to generate more hot electrons by a sufficientamount of electric field Ex of the channel horizontal direction toinduce the generated hot electrons to the dielectric film side by theelectric field Ey of the channel perpendicular direction high to acertain extent. At this point, if the electron density De is not high inplaces where the concentration of the electric field Ex of the channelhorizontal direction is the strongest, even if the probability ofgenerating hot electrons is high, the amount of electrons as the amountfor injection becomes less.

[0077] In FIG. 4, changes of the electric field Ex of the channelhorizontal direction is small so the electric field strength is low, andbecause the generating probability of hot electrons is low, chargeinjection efficiency is low.

[0078] In FIG. 4 to FIG. 6, changes of the electric field Ex of thechannel horizontal direction is the largest in FIG. 5, however, theelectric field Ey of the channel perpendicular direction is a low ofabout 1×10⁵ (V/cm), and therefore the injection efficiency of hotelectrons is considered not very high.

[0079] In FIG. 6, the concentration of the electric field Ex of thechannel horizontal direction is sufficient, and the electric field Ey ofthe channel perpendicular direction is 5×10⁵ to 6×10⁵ (V/cm), alsoreaching a sufficient level, whereby the highest injection efficiencycan be expected.

[0080] The prototype memory cell was produced on the basis of thecalculation results of the device simulation, and the writingcharacteristics of the memory cell were actually evaluated. Theevaluation results are shown in FIG. 7 to FIG. 9.

[0081]FIG. 7 is a graph of a conventional type memory cell, that is,results of measurements of the writing characteristics of a memory cellwherein a P-type semiconductor is directly under both the memory gate(word line) and control gate. This structure corresponds to the model ofFIG. 4 in the foregoing device simulation.

[0082]FIG. 8 and FIG. 9 are graphs of the memory cell of the presentembodiment, that is, results of measurements of the writingcharacteristics of a memory cell having directly under the memory gatean N-type accumulation layer-forming region having an inverse (areverse) polarity to the semiconductor directly under the control gate.In the memory cell used in the measurement of FIG. 9, similar to themodel of FIG. 5 in the foregoing device simulation, ion injection wasperformed twice under a dose amount of 7×10¹² cm⁻² and accelerationenergy of 7 keV to form the accumulation layer-forming regions ACLa,ACLb. In the memory cell used in the measurement of FIG. 9, the impurityconcentration of the accumulation layer-forming regions ACLa, ACLbdirectly under the memory gate is slightly lower than the case of FIG. 8and corresponds to the model of FIG. 6. In other words, the accumulationlayer-forming regions ACLa, ACLb were formed by performing ion injectiontwice under a dose amount of 3.5×10 ¹² cm⁻² and acceleration energy of 7keV.

[0083] Plotted in the graphs of FIG. 7 to FIG. 11 is a threshold voltagewhen an application duration of a writing pulse to be applied to thememory gate was changed in the range from 1×10 ⁻⁶ s (1 μS) to 1×10⁻² s(10 ms). Further, in each of the graphs of FIG. 7 to FIG. 11, a voltagevalue of a pulse for writing to be applied to the memory gate was causedto change from 2.5 V to 7.0 V with 0.5 V notch as a parameter, and eachof the threshold voltages Vth of the voltage value is connected by aline and shown as a curve line denoting the transition thereof.

[0084] Shown in FIG. 7 to FIG. 11 is a cell having a large variation inthe threshold voltage Vth in a region where a voltage value Vg of thewriting pulse is low and the application duration of the pulse is short,enabling high charge injection efficiency and high-speed operation.

[0085] In the voltage Vg of the curve line 7 V in FIG. 7, theapplication duration of the writing pulse was a shortest 1 μs and athreshold voltage Vth of 0.7 V was detected, and further, in order toobtain a 1.5 V threahold voltage Vth, the writing pulse voltage Vg mustbe made 7 V.

[0086] In the voltage Vg of the curve line 7 V in FIG. 8, theapplication duration of the writing pulse was 1 μs and a thresholdvoltage Vth of 0.8 V was detected. In a writing operation where Vg isequal to 7 V and a pulse application duration is 1 ms, a thresholdvoltage Vth of 1.9 V has been detected. This shows that the chargeinjection efficiency is higher than the example of FIG. 7 due toproviding the accumulation layer-forming regions ACLa.

[0087] In the voltage Vg of the curve line 7 V in FIG. 9, theapplication duration of the writing pulse was 1 μs and a large thresholdvoltage Vth of 1.4 V was detected. In a writing operation where Vg isequal to 7 V and a pulse application duration is 1 ms, a thresholdvoltage Vth varies until 2.45 V. This result shows that if the impurityconcentration of the accumulation layer-forming region ACLa isoptimized, the charge injection efficiency becomes considerably high.

[0088] These measurement results conform to the calculations from thedevice simulations results illustrated in FIG. 4 to FIG. 6. It is shownthat the memory cell comprising the accumulation layer-forming regionACLa illustrated in FIGS. 1 and 2 is more capable of higher chargeinjection efficiency and higher-speed and lower voltage operation thanthe memory cell without the accumulation layer-forming region ACLa.Further, to improve the charge injection efficiency as an aim to make amemory cell high-speed and low voltage, the impurity concentration ofthe accumulation layer-forming regions is reduced lower than theimpurity concentration of the source/drain regions S/D1, S/D2,indicating that an optimized value exist in the concentration thereof.

[0089] In the erasure operation, the charge held in the chargeaccumulation film is extracted or a charge having an inverse polarity tothat of the charge held in the charge accumulation film is injected.

[0090] In the case of extracting the held charges, there is a case ofextracting the charges to the word line side through the top potentialbarrier film TOP and a case of extracting the charges to the substrateside through the bottom potential barrier film BTM. In either case, inorder to generate electric field of the extracting direction, theoperation voltage controlling means 1, 2, and 3 applies a voltagebetween the word line WL and the source/drain region S/D1 or S/D2 inFIG. 1 (and between the word line WL and the substrate SUB). Due tothis, the held charges are extracted to the substrate side or the wordline side by FN tunneling or the like. When the held charges areextracted from the charge accumulation film, the memory transistorchanges to an erasure state.

[0091] Contrarily, as illustrated in FIG. 10, in the case of performingerasing by injecting into the storage 1 charges having an inversepolarity to that of held charges, a negative voltage is applied to theword line WL portion serving as the memory gate of the storage 1 sidewhile a positive voltage is applied to the source/drain region S/D1 ofthe storage 1 side. Under these conditions, an inversion layer is formedin the accumulation layer-forming region ACLa, and an avalanchebreakdown occurs due to a precipitous curving of an energy band. In thecourse leading up to the breakdown, high energy electrons, occurrence ofpairs of holes, and hot electrons are drawn to the positive voltage andabsorbed into the accumulation layer-forming region ACLa or thesource/drain region S/D1. A greater portion of the hot holes flows tothe substrate SUB, however, a portion thereof is drawn to the anelectric field by the memory gate and injected into the chargeaccumulation film GD (storage 1). Even in this erasure method, whenthere is a desire to inject the hot holes into the storage 2 of theopposite side, then similar electric field is caused to occur in thestorage 2 side. The erasing of data in the storage 2 can be performedindependently from the storage 1 and two bit erasure is also possible atthe same time.

[0092] In the reading operation, the so-called inversion read isemployed. In other words, the operation controlling means 1, 2 applies adrain voltage of about, for example, 1.5 to 3 V to between the twosource/drain regions S/D1, S/D2 and a predetermined positive voltage tothe control gate CL and the word line WL portion serving as the memorygate of the source side, respectively, so that the storage side holdingthe stored data intended for reading serves as a source while the otherstorage side serves as a drain. As a result, in response to whetherthere are charges in the source side storage intended for reading ornot, or a difference in the amount of charges, a channel is rendered ONor OFF or a difference in the amount of current flow occurs, resultingin the emergence of a potential variation in the source/drain region ofthe drain side. Reading of this potential variation by an unillustratedsense amplifier enables logical discrimination of the storage data.Reading of the other storage can be similarly performed by switching thesource and drain. Thus, two bit storage data can be read independently.

[0093] A sectional view of a word line direction of a memory cell as amodified example of the first embodiment is shown in FIG. 11A. FIG. 11Bis a view of an equivalent circuit of the memory cell.

[0094] A memory cell M′ is comprised of a two-transistor configurationwherein a memory transistor MT and the control transistor CT areconnected in series between the two lines of bit lines BLa, BLb. Thememory transistor MT, similar to the two memory transistors MT1, MT2illustrated in FIG. 1, is controlled by the word line WL.

[0095] In the sectional view structure of the memory cell M′, theaccumulation layer-forming region ACLb is not formed therein as in thesectional view structure of the memory cell illustrated in FIG. 2A, butinstead the source/drain region S/D2 is provided in the substrate regionnear an edge of the control gate (control line) CL and there is notformation of the charge accumulation film GD at the side surface of thecontrol gate CL of the source/drain region S/D2 side. The accumulationlayer-forming region ACLa of the source/drain region S/D1 side has thesame impurity concentration and depth as the accumulation layer-formingregion ACLa shown in FIG. 2A. The memory cell shown in FIG. 11A storesone bit data, however, the dimension of the memory cell is smaller thanthe dimension of the memory cell for two bit storage illustrated in FIG.2A.

[0096] Second Embodiment

[0097]FIG. 12 is a view of an equivalent circuit of a non-volatilememory cell as a second embodiment of the non-volatile semiconductormemory device of the present invention.

[0098] In a memory cell 2 shown in FIG. 12, a gate of a controltransistor CT is controlled by a word line WL, a gate of the memorytransistor MT1 is controlled by a first control line CLa, and a gate ofa memory transistor MT2 is controlled by a second control line CLb.

[0099] An operation voltage is controlled at the time of writing,erasing and reading data, and a column operation controlling means 1 forcontrolling the bit lines BLa, BLb and control lines CLa, CLb, a rowoperation controlling means 2 for controlling the word line WL, and asubstrate voltage controlling means 3 for controlling the application ofa voltage to the substrate are provided as operation controlling meanssupplied to the memory cell 2.

[0100]FIG. 13A is a schematic sectional view in a direction along a wordline of the memory cell shown in FIG. 12, and FIG. 13B is a plane viewthereof.

[0101] In the memory cell, similar to the illustrations of FIGS. 2A and2B, source/drain regions S/D1, S/D2, and accumulation layer-formingregions ACLa, ACLb are formed in a surface region of a substrate SUB. Asurface region of the substrate SUB between the accumulationlayer-forming regions ACLa, ACLb serves as an inversion layer-formingregion CH1.

[0102] On the inversion layer-forming region CH1 is formed a gateinsulating film GD0 having a width narrower than the width of theinversion layer-forming region CH1, and a word gate electrode WG isformed on the gate insulating film GD0. The word gate electrode WG,comprised of for example polycrystalline silicon or amorphous silicondoped with impurities, is formed having the same width as that of theword line WL and as an isolated pattern in every memory cell. In FIG.13A, the inversion layer-forming region CH1, the accumulationlayer-forming regions ACLa, ACLb, the gate insulating film GD0, and theword gate electrode WG forms the control transistor CT shown in FIG. 12.

[0103] A bottom potential barrier film BTM is formed covering the twoside surfaces of the word gate electrode WG facing each other in thechannel direction, a surface of the inversion layer-forming region CH1where the gate insulating film GD0 is not formed, surfaces of theaccumulation layer-forming regions ACLa, ACLb and surfaces of thesource/drain regions S/D1, S/D2. A charge trap film CHS is formed on thebottom potential barrier film BTM, and a top potential barrier film TOPis further formed on the charge trap film CHS. The bottom potentialbarrier film BTM, the charge trap film CHS, and the top potentialbarrier film TOP comprises a charge accumulation film GD having a chargeaccumulation faculty.

[0104] The control lines CLa, CLb having for example a ¼ circular shapesectional surface is formed in the regions located above theaccumulation layer-forming regions ACLa, ACLb on top of the toppotential barrier film TOP of the side surfaces of the word gateelectrode WL. The control lines CLa, CLb are comprised ofpolycrystalline silicon or amorphous silicon doped with impurities. Thecontrol lines CLa, CLb are embedded in an interlayer insulating layerINT and arranged parallelly in the row direction. In FIG. 12, thecontrol lines CLa, CLb are gate electrodes of the memory transistors MT1and MT2.

[0105] The word line WL electrically connected to the word gateelectrode WG is formed on the interlayer insulating layer INT.

[0106] In the memory cell M, the control transistor CT operatessecondarily in order to improve the charge injection efficiency at thewriting or erasing time of the memory transistors MT1, MT2. Further, dueto the existence of the control transistor CT, regions for injectingcharges are limited. That is, a storage 1 for injecting charges in thememory transistor MT1 is limited by a portion of the charge accumulationfilm GD on top of the accumulation layer-forming region ACLb, and astorage 2 for injecting charges in the memory transistor MT2 is limitedby a portion of the charge accumulation film GD on top of theaccumulation layer-forming region ACLa. The single-layered gateinsulating film GD0 located between the storage 1 and the storage 2 doesnot have a charge accumulation faculty, so it cannot contribute to datastorage. Furthermore, due to the existence of the control transistor CT,the charges injected into the memory transistors MT1, MT2 located onboth sides thereof do not interfere among each other, and therefore twobit storing can be surely performed to the two memory transistors MT1,MT2.

[0107] A sectional view of a word line direction of the memory cell as amodified example of the seond embodiment is shown in FIG. 14A. FIG. 14Bis a view of an equivalent circuit of the memory cell.

[0108] A memory cell M2′ is comprised of a two-transistor configurationwherein the memory transistor MT and the control transistor CT areconnected in series between the two lines of bit lines BLa, BLb. Thememory transistor MT, similar to the memory transistors MT1 illustratedin FIG. 12, is controlled by the control line CLa.

[0109] In the sectional view structure of the memory cell M2′, theaccumulation layer-forming region ACLb is not formed therein as in thesectional view structure of the memory cell illustrated in FIG. 13A, butinstead the source/drain region S/D2 is provided in the substrate regionnear an edge of the word gate electrode WG and there is no formation ofthe charge accumulation film GD at the side surface of the word gateelectrode WG of the source/drain region S/D2 side. The accumulationlayer-forming region ACLa of the source/drain region S/D1 side has thesame impurity concentration and depth as the accumulation layer-formingregion ACLa shown in FIG. 13A. The memory cell shown in FIG. 14A storesone bit data, however, the dimension of the memory cell is smaller thanthe dimension of the memory cell for two bit storage illustrated in FIG.13A.

[0110] Third Embodiment

[0111] A third embodiment relates to a charge injection method forefficiently injecting holes at the time of erasing without using anegative voltage.

[0112]FIG. 15 is a view showing an erasure operation. A structuresimilar to the structure illustrated in FIG. 3A is shown. FIG. 16 is achart showing erasure bias conditions. As an erasure operation, twomodes (mode 1-1, mode 1-2) utilizing ionization colliding and a mode 2utilizing inter-band tunneling are shown.

[0113] First, the mode 1-1 will be explained.

[0114] In the erasure of the mode 1-1, the operation voltage controllingmeans 1, 2, and 3 renders a source voltage Vs to be applied to thesource/drain region S/D2 serving as a source, a substrate voltage Vsubto be applied to the substrate (first conductivity type semiconductor)SUB, and an erasure gate voltage Vmg to be applied to the word line WLall into a reference potential Vss (for example, 0 V). Under this state,the column operation controlling means 1 applies a predeterminedpositive voltage (drain voltage Vd=7 to 8 V) to the source/drain regionS/D1 serving as a drain, and a predetermined positive voltage Vcg=3 to 5V to the control gate CL as a controlling gate voltage for forming achannel in the inversion layer-forming region CH1.

[0115] Under this bias condition, an electron e traveling in the formedchannel from the left to the right direction of FIG. 15 is acceleratedby an electric field in the lateral direction, and a portion thereofbecomes hot electrons. However, different from the first embodiment,because the memory gate (word line) is not biased with a positivevoltage, most of the electrons are not injected into the chargeaccumulation film GD but while being further accelerated, a portion ofthe electrons travels around to a region below the accumulationlayer-forming region ACLa avoiding the highly resistant accumulationlayer-forming region ACLa in a state without a accumulation film formedtherein while the rest enters the accumulation layer-forming regionACLa. The high energy electrons that have entered a depletion layerdirectly under the accumulation layer-forming region ACLa or into theaccumulation layer-forming region ACLs collide with silicon lattices orare subjected to dispersion, thereby generating a pair of high energyhole HH and electron HE. Between the high energy hole HH and electronHE, the hot electron HE is absorbed by the N-type source/drain regionS/D1 or the accumulation layer-forming region ACLa, whereas the hot holeHH drifts to a center side of the channel forming region CH1, while aportion thereof heads for the word line WL portion above thesource/drain region S/D1 along a recess of a potential at a boundary ofthe substrate SUB and the accumulation layer-forming region ACLa. Thehot hole exceeds the potential barrier of the bottom film BTM and iscaptured by a carrier trap inside the charge trap film CHS. Thecapturing region of these charges (storage 1) is limited by a portion ofthe drain S/D1 side.

[0116]FIG. 7 is a view showing simulation results of an ionizationcolliding erasure of the mode 1-1. In this simulation, an energydistribution per unit volume in a given unit time is obtained bycalculation under the conditions in which the source/drain region S/D2serving as the source, the substrate SUB, and the word line WL portionserving as the memory gate are provided and a voltage of 7 V is appliedto the source/drain region S/D1 serving as the drain and a voltage of 5V to the control gate CL. FIG. 17 shows a cross-sectional view of aportion of a drain side of an element cut across a channel direction,and a vertical and lateral scale per unit thereof is 0.1 m. A numericalvalue in FIG. 17 is an exponent value expressing high energy chargedensity, for example, 1×10²⁶/cm³ or greater of high energy charges existin the inner side of the numerical value 26.

[0117]FIG. 18 is a view showing a case of a high-energy chargedistribution of an element under the same bias conditions as the exampleillustrated in FIG. 17 without the provision of the accumulationlayer-forming regions ACLa.

[0118] From comparing the illustrations of FIG. 17 and FIG. 18, it waslearned that by providing the accumulation layer-forming region ACLa,the probability of generating high energy charges is about 10⁹ to 10¹⁰higher. Further, in the case of FIG. 18, though a distribution center ofcomparatively high energy charges is a substrate surface side adjacentto the source/drain region S/D1 serving as the drain, in the case ofFIG. 16 where the accumulation layer-forming region ACLa is provided,the distribution center thereof ranges from the entire region of theaccumulation layer-forming region ACLa to a deep portion of thesubstrate down below. This indicates that the ionization colliding notonly occurs in the accumulation layer-forming region ACLa, but also inthe depletion layer below the accumulation layer-forming region ACLa.Thus, this supports the prediction that a good amount of high energycharges are generated.

[0119] Based on such simulation results, the impurity concentration anddepth of the accumulation layer-forming region ACL were determined toproduce a prototype element. Thereafter, a threshold voltage variationwas measured by injecting electrons of a quantity enabling obtainment ofa predetermined threshold voltage variation into the storage 1 of thecharge accumulation film GD of the element by the CHE injection, andinjecting hot holes generated by the ionization colliding into thecharge accumulation film GD while diversely changing a pulse durationfor applying a drain voltage, that is, the so-called inversion readmethod. The result of this measurement is shown in FIG. 19.

[0120] In this measurement, a measurement of a writing side at athreshold measurement after the first pulse application could not bemeasured, however, a threshold voltage variation of 2 V or more from anerasure state was already achieved in a short time erasure of 2 μs. Thusit became clear that extremely high-speed erasure is possible if theionization colliding is utilized.

[0121] As a reference, a conventional FN tunneling erasurecharacteristic is shown in FIG. 20. The sample (non-volatile memorydevice) used in this measurement has a split gate structure, however, itdoes not have a low concentrated impurity region (accumulationlayer-forming region ACLa) as the present embodiment. At the time oferasing, close to −10 V of negative voltage is applied to the memorygate to extract the accumulated charges to the substrate side by FNtunneling. Or, under a state where a predetermined voltage is applied tothe control gate, a negative bias is applied to the memory gate. Theseerasure methods are the same as the first embodiment, and thereforedetails thereof will be omitted here.

[0122] In the measurement of the erasure characteristic of FIG. 20, theabove FN tunneling erasure was used. Further, a pulse applicationduration dependency of a threshold voltage was examined by changing theimpress voltage of the memory gate from −4.0 V to −9.0 V. In the FNtunneling erasure, almost all the threshold voltages do not vary in theshort time erasure of 2 μs. If trying to obtain a threshold voltagevariation of 2 V or more, 10 ms or greater is required even if theimpress voltage of the gate is a high voltage of −9 V, and therefore theerasure operation is extremely slower than the erasure time of 2 μs bythe ionization colliding erasure of the present embodiment.

[0123] In the present embodiment, also with the aim to examine arelationship between the depth of the accumulation layer-forming regionACLa and the generation probability of high energy charges at the timeof test production, the energy at the time of ion injection wasdiversely changed. The relationship between the ion injection energy anderasure characteristics is shown in FIG. 20. Shown in FIG. 21 aresamples of a drain voltage dependency of threshold voltages 7 keV, 15keV, and 25 keV as the energy of ion injection. Among these, the ioninjection energy of 15 keV is fastest for erasure of an element, slowingdown at 25 keV and 7 keV in that order. Namely, there is an optimalvalue for the depth of the accumulation layer-forming region ACLa, thatis, it is not good if too shallow or too deep. If the accumulationlayer-forming region is too shallow, the high energized electrons willbe injected, thereby inhibiting the reduction of the threshold voltage.Contrarily, if too deep, the generation probability of hot electrons isreduced or it indicates that the injection of holes is not progressingefficiently due to the fact that the source of generating hot electronsis too far from the substrate surface.

[0124] In the mode 1-2 of FIG. 16, ionization colliding erasure isperformed under a state where the substrate is not applied with avoltage by the substrate voltage controlling means 3 but is in an openstate (floating state). At this point, the other bias conditions are setthe same as those of the above mode 1-1. In the ionization collidingerasure, a considerable amount of hot holes are generated in one timeand a large portion thereof flows to the substrate. Therefore, to reducethe current load of peripheral circuits by suppressing a substratecurrent, it is preferable that the substrate is electrically renderedinto a floating state as such. Further, if the substrate is renderedinto an open state, only the electric field between the drain and memorygate generates holes. Therefore, the generated hot holes are efficientlyinjected into the charge trap film CHS. In this case, if the substrateor well potential varies at all, fluctuation may possibly occur in theerasure speed. However, since the erasure speed is an extremely shorttime, influences thereto are thought to be small, and therefore it ispossible to sufficiently erase all the object cells by optimizing theerasure speed.

[0125] Different from the other modes 1-1 and 1-2 explained above, themode 1-2 utilizes hot holes generated due to the inter-band tunnelcurrent. In this erasure method, though described in detail in the firstembodiment, only a reference potential and a positive voltage is usedhere whereas a negative voltage is not used. In other words, 8 to 9 V ofthe positive voltage Vd is applied to the drain under a state where thesource is rendered open and the substrate potential Vsub, theapplication voltages Vmg and Vcg of the memory gate and the control gateare all held at a reference potential. Due to an electric field betweenthe drain and the memory gate, a deep depletion layer is formed on thesurface of the source/drain region S/D1 functioning as a drain and theaccumulation layer-forming region ACLa whereby an inter-band tunnelingcurrent is generated due to a precipitous bending of the energy band. Apair of hot electron and hot hole is generated due to this, and betweenthe two, the hot hole is injected into the charge trap film CHS of thecharge accumulation film GD.

[0126] The electric field generating hot holes caused by such inter-bandtunneling or ionization colliding is lower compared with the electricfield necessary for simply extracting the electrons from inside theentire surface of the channel using the FN tunneling. Further, since anegative voltage is not used, the peripheral circuits can be simplified,and is suitable for a non-volatile memory in which affinity of theprocess thereof with logic circuits intermixedly installed in a systemLSI or the like is demanded.

[0127] Various modifications may be made to the first to thirdembodiments of the present invention.

[0128] The structure of the charge accumulation film GD is not limitedto the so-called MONOS type EEPROM, but may be the MNOS type EEPROM.Further, the present invention is applicable to small size conductors,for example, nanocrystal types having particles of polycrystallinesilicon dispersed and embedded inside the dielectric film, or furtherthe so-called FG type EEPROM.

[0129] In the memory cell M illustrated in FIG. 2A, the memory cell M′illustrated in FIG. 11A, the memory cell M2 illustrated in FIG. 13A, andthe memory cell 2′ illustrated in FIG. 14A, the gate electrode may beformed singularly. The present invention has an accumulationlayer-forming region, and controlling the concentration and depththereof enables the gate impress voltages of the memory transistor andthe control transistor to be made equivalent. In this case, an advantageof simplifying the element structure can be obtained.

[0130] According to the non-volatile semiconductor memory circuit of thepresent invention, since the non-volatile semiconductor memory circuitcomprises a channel structure capable of easily generating a highelectric field required in the source side injection, the source sideinjection efficiency is improved. Due to this, a writing or erasing timeis shortened. Or, it became possible to reduce an impress voltage andconsumption power necessary for writing or erasing.

[0131] According to the operation of the non-volatile semiconductormemory circuit of the present invention, a high electric field requiredin the source side injection is easily generated, and since the chargeinjection efficiency is high by a charge injection operation using thehigh electric field, high-speed and low consumption power data storagecan be performed. At the time of the above charge injection and wheninjecting charges having a reverse polarity, utilizing the ionizationcolliding or inter-band tunneling current enables high energy electronsto be generated without using a negative voltage. Therefore, peripheralcircuits can be simplified. Due to this, a data system integrated withother logic circuits, etc. can utilize the present invention.

INDUSTRIAL APPLICABILITY

[0132] The non-volatile memory device of the present invention can beused as a memory of a variety of electronic devices.

1. A non-volatile semiconductor memory device comprising: a firstconductivity type semiconductor substrate (SUB); a first conductivitytype inversion layer-forming region (CH1) defined in a surface region ofsaid semiconductor substrate (SUB), a channel being formed by aninversion layer therein; second conductivity type accumulationlayer-forming regions (ACLa, ACL2 b) formed at least at one side of saidinversion layer-forming region (CH1) in the surface region of saidsemiconductor substrate (SUB), channels being formed by accumulationlayers therein; a channel-forming region (CH) including said inversionlayer-forming region (CH1) and said accumulation layer-forming regions(ACLa, ACLb); a first second conductivity type region (S/D1) formed atone side of said channel forming region (CH) in the surface region ofsaid semiconductor substrate (SUB); a second second conductivity typeregion (S/D2) formed at other side of said channel forming region (CH)in the surface region of said semiconductor substrate (SUB); aninsulating film (GD0) formed on said inversion layer-forming region(CH1); a first conductive layer (CL) formed on said insulating film(GD0); a charge accumulation film (GD) having a charge accumulationfaculty formed on an upper surface of said first conductive layer (CL),a side surface of a stacked portion of said insulating film (GD0) andsaid first conductive layer (CL), an exposure surface of said inversionlayer-forming region (CH1), an upper surface of said accumulationlayer-forming regions (ACLa, ACLb), and an upper surface of said firstand second second conductivity type regions (S/D1, S/D2); and a secondconductive layer (WL) formed on said charge accumulation film (GD), saidsecond conductive layer (WL) being connected to a word line, and saidfirst and second second conductivity type regions (S/D1, S/D2) beingconnected to bit lines (Bla, BLb).
 2. A non-volatile semiconductormemory device as set forth in claim 1, wherein an impurity concentrationof said accumulation layer-forming regions (ACLa, ACLb) is lower than animpurity concentration of said first and second second conductivity typeregions (S/D1, S/D2).
 3. A non-volatile semiconductor memory device asset forth in claim 1, wherein: two of said accumulation layer-formingregions (ACLa, ACLb) are formed at both sides of said inversionlayer-forming region (CH1); a control transistor (CT) is formed by saidinversion layer-forming region (CH1), said two accumulationlayer-forming regions (ACLa, ACLb), said insulating film (GD0), and saidfirst conductive layer (CL); a first memory transistor (MT1) is formedby one of said two accumulation layer-forming regions (ACLa), saidinversion layer-forming region (CH1), said first second conductivitytype region (S/D1), said charge accumulation film (GD), and said secondconductive layer (WL); and a second memory transistor (MT2) is formed bythe other of said two accumulation layer-forming regions (ACLb), saidinversion layer-forming region (CH1), said second second conductivitytype region (S/D2), said charge accumulation film (GD), and said secondconductive layer (WL).
 4. A non-volatile semiconductor memory device asset forth in claim 1, wherein: one of said accumulation layer-formingregion (ACLa) is formed between said inversion layer-forming region(CH1) and said first second conductivity type region (S/D1); a controltransistor (CT) is formed by said inversion layer-forming region (CH1),said accumulation layer-forming region (ACLa), said first secondconductivity type region (S/D1), said insulating film (GD0), and saidfirst conductive layer (CL); and a memory transistor (MT1) is formed bysaid accumulation layer-forming region (ACLa), said inversionlayer-forming region (CH1), said first second conductivity type region(S/D1), said charge accumulation film (GD), and said second conductivelayer (WL).
 5. A non-volatile semiconductor memory device as set forthin claim 1, wherein said charge accumulation film (GD, BTM, CHS, TOP) isformed by stacking the following: a first potential barrier film (BTM)formed covering an upper surface of said first conductive layer (CL), aside surface of a stacked portion of said insulating film (GD0) and saidfirst conductive layer, an exposure surface of said inversionlayer-forming region (CH1), an upper surface of said accumulationlayer-forming regions (ACLa, ACLb), and upper surfaces of said first andsecond second conductivity type regions (S/D1, S/D2); a charge trap film(CHS) formed on said first potential barrier film (BTM), and a secondpotential barrier film (TOP) formed on said charge trap film CHS forimparting a deep charge capturing level in the vicinity of an interfacewith said charge trap film.
 6. A non-volatile semiconductor memorydevice as set forth in claim 1, wherein a thickness of said secondpotential barrier film (TOP) is defined as a thickness for preventinginjection of a hole from said second conductive layer (WL).
 7. Anon-volatile semiconductor memory device as set forth in claim 1,wherein a width of said first conductive layer (CL) has a length whereina carrier supplied from one of said second conductivity type region(S/D2) travels ballistically or semi-ballistically in said inversionlayer-forming region (CH1).
 8. A non-volatile semiconductor memorydevice as set forth in claim 1, further comprising an operationcontrolling means, said operation controlling means performs thefollowing operation at the time of writing or erasing data: applying adrain voltage to one of said first and second second conductivity typeregion (S/D1) and a reference voltage to the other (S/D2) thereof, andapplying a first gate voltage to said second conductive layer (WL) and asecond gate voltage lower than said first gate voltage to said secondconductive layer (CL) so that a charge energetically excited in saidinversion layer-forming region (CH1) near an interface with saidaccumulation layer-forming region (ACLa) is injected into said chargeaccumulation film (GD) under said second conductive layer (WL) from theother said second conductively type region (S/D2) applied with saidreference voltage at the time of writing or erasing data.
 9. Anon-volatile semiconductor memory device as set forth in claim 1,further comprising an operation controlling means, said operationcontrolling means performs the following operation at the time ofwriting or erasing data: applying a drain voltage to one of said firstand second second conductivity type region (S/D1) and a referencevoltage to the other (S/D2) thereof; and applying an optimized voltageto said first conductive layer (CL) and said second conductive layer(WL), respectively, so that a carrier supplied to said inversionlayer-forming region (CH1) traveling in a formed inversion layer isaccelerated, and the accelerated high energy carrier is caused tocollide with a semiconductor lattice at said accumulation layer-formingregion (ACLa) side to thereby generate a pair of electron and electronhole by ionization at the time of collision, whereby the generatedelectron hole is injected into said charge accumulation film (GD) belowsaid second conductive layer (W).
 10. A non-volatile semiconductormemory device as set forth in claim 1, further comprising an operationcontrolling means, said operation controlling means performs thefollowing operation, at the time of writing or erasing data: applying areference voltage to said first and second conductive layers (CL, WL)and said semiconductor substrate (SUB); rendering one of said first andsecond second conductivity type regions (S/D2) into an electricallyfloating state and forming a depletion layer in the other said secondconductivity type region (S/D1); generating a pair of electron andelectron hole by inter-band tunneling in the formed depletion layer; andhaving the generated electron hole apply a value of a positive voltageinjected into said charge accumulation film (GD) to the other of saidfirst and second second conductivity type regions (S/D1).
 11. Anon-volatile semiconductor memory device comprising: a firstconductivity type semiconductor substrate (SUB); a first conductivitytype inversion layer-forming region (CH1) defined in a surface region ofsaid semiconductor substrate (SUB), channels being formed by aninversion layer therein; second conductivity type accumulationlayer-forming regions (ACLa, ACL2 b) formed at least at one side of saidinversion layer-forming region (CH1) in a surface region of saidsemiconductor substrate (SUB), channels being formed by accumulationlayers therein; a channel forming region (CH) including said inversionlayer-forming region (CH1) and said accumulation layer-forming regions(ACLa, ACLb); a first second conductivity type region (S/D1) formed atone side of said channel forming region (CH) in the surface region ofsaid semiconductor substrate (SUB); a second second conductivity typeregion (S/D2) formed at other side of said channel forming region (CH)in the surface region of said semiconductor substrate (SUB); aninsulating film (GD0) formed on said inversion layer-forming region(CH1); a first conductive layer (WG) formed on said insulating film(GD0); a charge accumulation film (GD) having a charge accumulationfaculty formed on a side surface of a stacked portion of said firstconductive layer (WG) and said insulating film (GD0), an exposuresurface of said inversion layer-forming region (CH1), an upper surfaceof said accumulation layer-forming regions (ACLa, ACLb), and an uppersurface of said first and second second conductivity type regions (S/D1,S/D2); and second conductive layers (CLa, CLb) formed on said chargeaccumulation film (GD) at a location above said accumulationlayer-forming regions (ACLa, ACLb), said first conductive layer (WG)being connected to a word line, and said first and second secondconductivity type regions (S/D1, S/D2) being connected to bit lines(Bla, BLb).
 12. A non-volatile semiconductor memory device as set forthin claim 11, wherein an impurity concentration of said accumulationlayer-forming regions (ACLa, ACLb) is lower than an impurityconcentration of said first and second second conductivity type regions(S/D1, S/D2).
 13. A non-volatile semiconductor memory device as setforth in claim 11, wherein: two of said accumulation layer-formingregions (ACLa, ACLb) are formed at both sides of said inversionlayer-forming region (CH1); a control transistor (CT) is formed by saidinversion layer-forming region (CH1), said two accumulationlayer-forming regions (ACLa, ACLb), said insulating film (GD0), and saidfirst conductive layer (WG); a first memory transistor (MT1) is formedby one of said two accumulation layer-forming regions (ACLa), saidinversion layer-forming region (CH1), said first second conductivitytype region (S/D1), said charge accumulation film (GD), and said secondconductive layer (CLa); and a second memory transistor (MT2) is formedby the other of said two accumulation layer-forming regions (ACLb), saidinversion layer-forming region (CH1), said second second conductivitytype region (S/D2), said charge accumulation film (GD), and said secondconductive layer (CLb).
 14. A non-volatile semiconductor memory deviceas set forth in claim 11, wherein: one of said accumulationlayer-forming region (ACLa) is formed between said inversionlayer-forming region (CH1) and said first second conductivity typeregion (S/D1); a control transistor (CT) is formed by said inversionlayer-forming region (CH1), said accumulation layer-forming region(ACLa), said first second conductivity type region (S/D1), saidinsulating film (GD0), and said first conductive layer (WG); and amemory transistor (MT1) is formed by said accumulation layer-formingregion (ACLa), said inversion layer-forming region (CH1), said firstsecond conductivity type region (S/D1), said charge accumulation film(GD), and said second conductive layer (CLa).
 15. A non-volatilesemiconductor memory device as set forth in claim 11, wherein saidcharge accumulation film (GD, BTM, CHS, TOP) is formed by stacking thefollowing: a first potential barrier film (BTM) formed on a side surfaceof a stacked portion of said first conductive layer (WG) and saidinsulating film (GD0), an exposure surface of said inversionlayer-forming region (CH1), an upper surface of said accumulationlayer-forming regions (ACLa, ACLb), and an upper surface of said firstand second second conductivity type regions (S/D1, S/D2); a charge trapfilm (CHS) formed on said first potential barrier film (BTM), and asecond potential barrier film (TOP) formed on said charge trap film CHSfor imparting a deep charge capturing level in the vicinity of aninterface with said charge trap film.
 16. A non-volatile semiconductormemory device as set forth in claim 11, wherein a thickness of saidsecond potential barrier film (TOP) is defined as a thickness forpreventing injection of a hole from said second conductive layer (WL).17. A non-volatile semiconductor memory device as set forth in claim 11,wherein a width of said first conductive layer (WG) has a length whereina carrier supplied from one of said second conductivity type region(S/D2) travels ballistically or semi-ballistically inside said inversionlayer-forming region (CH1).
 18. A non-volatile semiconductor memorydevice as set forth in claim 11, further comprising an operationcontrolling means, said operation controlling means performs thefollowing operation, at the time of writing or erasing data: applying adrain voltage to one of said first and second second conductivity typeregions (S/D1) and a reference voltage to the other (S/D2) thereof, andapplying a first gate voltage to said second conductive layer (CLa) anda second gate voltage lower than said first gate voltage to said secondconductive layer (WG) so that a charge energetically excited in saidinversion layer-forming region (CH1) near an interface with saidaccumulation layer-forming region (ACLa) is injected into said chargeaccumulation film (GD) under said second conductive layer (CLa) from theother said second conductively type region (S/D2) applied with saidreference voltage.
 19. A non-volatile semiconductor memory device as setforth in claim 11, further comprising an operation controlling means,said operation controlling means performs the following operation, atthe time of writing or erasing data: applying a drain voltage to one ofsaid first and second second conductivity type region (S/D1) and areference voltage to the other (S/D2) thereof, and applying an optimizedvoltage to said first conductive layer (CL) and said second conductivelayer (WL), respectively, so that a carrier supplied to said inversionlayer-forming region (CH1) traveling in a formed inversion layer isaccelerated, and the accelerated high energy carrier is caused tocollide with a semiconductor lattice at said accumulation layer-formingregion (ACLa) side to thereby generate a pair of electron and electronhole by ionization at the time of collision, whereby the generatedelectron hole is injected into said charge accumulation film (GD) belowsaid second conductive layer (WL).
 20. A non-volatile semiconductormemory device as set forth in claim 1, further comprising an operationcontrolling means, said operation controlling means performs thefollowing operation at the time of writing or erasing data: applying areference voltage to said first and second conductive layers (MG, CLa,CLb) and said semiconductor substrate (SUB); rendering one of said firstand second second conductivity type regions (S/D2) to an electricallyfloating state and forming a depletion layer in the other said secondconductivity type region (S/D1); generating a pair of electron andelectron hole by inter-band tunneling in the formed depletion layer; andhaving the generated electron hole apply a value of a positive voltageinjected into said charge accumulation film (GD) to the other of saidfirst and second second conductivity type regions (S/D1).